1. Field of the Invention
The present invention relates to a display apparatus having a thin film transistor (which will be referred to hereinafter as a TFT), for example, as a switching element, which is especially suitable for application to a liquid crystal display apparatus.
2. Related Background Art
A display apparatus using liquid crystal generally has a structure in which a displaying material such as liquid crystal is filled between two insulating substrates facing each other, and a voltage is selectively applied to the displaying material. At least one of the insulating substrates is a substrate on which a switching element such as a TFT and a pixel electrode connected to the switching element are formed, which will be referred to hereinbelow as an array substrate. On the array substrate, signal lines (source lines and gate lines) for transmitting signals to the switching element are formed like a matrix.
FIG. 11 shows a plan view of an array substrate in a conventional display apparatus, and FIG. 12 shows a cross-sectional view along line B-B in FIG. 11. In FIG. 11 and FIG. 12, a reference symbol 1 denotes an insulating substrate, 2 denotes a gate line, 3 denotes a gate insulating film, 4 denotes a semiconductor layer as a channel, 5 denotes an ohmic contact layer, 6 denotes a source electrode, 7 denotes a passivation film as an overcoating insulating film, 8 denotes a contact hole formed in an insulating layer, 9 denotes a pixel electrode, 10 denotes a drain electrode, 11 denotes an extending pattern of the drain electrode, and 13 denotes a source line. The substrate is formed as in the following.
First, a first conductive film is deposited on the insulating substrate 1. Next, the gate line 2 is formed by patterning in photoengraving and etching processes.
Then, the gate insulating layer 3 which is a first insulating layer, the non-doped semiconductor layer 4, and a doping semiconductor layer which will be the ohmic contact layer 5 are deposited successively. Further, a semiconductor pattern 4 and 5 which lie below a channel of a TFT and the source line 13, both of which will be formed later are configured by exposure and development of photoengraving processes and etching processes.
Then, a conductive layer such as Cr and Al is deposited, and by exposure and development of photoengraving processes and etching processes, the source line 13, the source electrode 6 of the TFT, the drain electrode 10, and the extending pattern 11 of the drain electrode are formed.
Furthermore, after depositing the passivation film 7 which is an insulating film such as SiN, exposure and development processes are carried out to form the contact hole 8 which is a continuity for a transparent conductive film which will be formed later, the source electrode 6, a drain electrode 10 pattern, and a gate line 2 pattern. The diameter of the contact hole 8 is preferably larger in order to reduce contact resistance.
Then, after the transparent conductive film such as ITO is deposited, the pixel electrode 9 is formed by exposure and development of photoengraving processes, and etching processes. By the above processes, a fabrication of the array substrate of a so-called bottom-gate type in which the semiconductor layer 4 is formed above the gate electrode is completed.
In the above processes, it is also possible to carry out exposure and development of photoengraving processes and etching processes after depositing the gate insulating layer 3 being the first insulating layer, the non-doped semiconductor layer 4, and the doping semiconductor layer which will be the ohmic contact layer 5, and further successively depositing conductive layers 6, 10, 11, and 13, which are Cr and Al, for example. In this way, formation of the source line 13, the source electrode 6 of the TFT, and the drain electrode 10 pattern, and formation of the semiconductor layer 4 pattern below those patterns can be done in one photoengraving process. In the array substrate fabricated in this procedure, the semiconductor layer 4 lies in nearly all the region below the conductive layer having the source electrode 6, the drain electrode 10, and so on.
In the array substrate fabricated in the process explained in the foregoing, the semiconductor layer 4 lies in all or part of the region below the source line 13, the source electrode 6 of the TFT, and the drain electrode 10. Especially, in the configuration where the semiconductor layer 4 lies in nearly all the region below the source electrode 6 and the drain electrode 10, the area becomes larger. When the etching quantity of a metal pattern forming the source electrode 6 and the drain electrode 10 is large, a pattern of the semiconductor layer 4 can project from a pattern of the source electrode 6 or of the drain electrode 10.
However, in the above-mentioned related art, when lights from a backlight come to the remaining semiconductor layer, electric charge is induced in the semiconductor layer. In this condition, the electric charge stored in the pixel electrode comes into the semiconductor layer (channel) of a TFT section through a carrier which is developed below the drain electrode. Further, when the lights from the backlight come to the semiconductor layer around a crossing point of the source line and the gate line, the electric charge (a carrier) in the semiconductor layer (a channel) of the TFT section flows into the source line through a carrier which is developed in the semiconductor layer below the source line. Due to the flowing out of the electric charge of the pixel electrode into the source line as described above, deterioration of display performance such as uneven brightness and/or reduced contrast occurs.
One solution for this problem is to shield the semiconductor layer below the drain electrode or the source line from lights with an extending pattern of the gate line or the gate electrode. This way, however, increases an overlapping area of the gate electrode or the gate line and the drain electrode, or of the gate line and the source line. Consequently, the capacity of the gate line and the source line becomes large; leading to significantly delay in the lines and greater pixel (drain) potential fluctuation generated in accordance with the gate electrode potential fluctuation, to cause the problem of noticeable uneven picture or screen flicker, which decreases picture quality. In the case of an array substrate in a display apparatus in which a semiconductor layer lies in all the region below a drain electrode, the area of a gate line and a gate electrode to shield the semiconductor layer from lights is still larger, which leads to more serious decrease in picture quality. A configuration for a different purpose from the present invention is disclosed in Japanese Patent Application Laid-Open No. S60-207116. FIG. 13A shows a plan view of a conventional array substrate in the above application, and FIG. 13B shows a sectional view of the same. In FIG. 13A and FIG. 13B, the same elements as in the FIG. 11 and FIG. 12 are denoted by the same reference symbols, and the reference symbol 21 denotes a light-shielding electrode, 22 denotes a thin film transistor, and 23 denotes a charge storage capacity. As shown in FIG. 13A and FIG. 13B, the charge storage capacity 23 is divided into several parts in the related art. Each of the divided charge storage capacity complements a mask mis-alignment in each other. Therefore, the total of the charge storage capacity is constant, and the area where the pixel electrode is covered by the light-shielding electrode is also constant. Accordingly, aperture ratio is constant as well, arising no unevenness of electric performance. As shown in FIG. 13B, the related art employs an array substrate of a so-called top-gate type in which the gate electrode 9 is arranged above the source electrode and the drain electrode. In this structure, since the semiconductor layer is arranged above the source electrode and the drain electrode, the problem caused by increase in leakage current due to lights from a backlight is not likely to occur, and because the light-shielding electrode 21 which doubles as a storage capacity line blocks lights at the base of the source line and so on, the capacity of the source line and the storage capacity line increases to cause delay in the lines, thereby decreasing picture quality. Also, when the source line and the storage capacity line are short-circuited due to contaminants produced during manufacturing processes and so on, picture problems such as line defects occur to lower manufacturing yield.
Another solution for the problems is disclosed in Japanese Patent Application Laid-Open No. H09-90409. FIG. 14 shows a sectional view of a conventional array substrate in the above application. In FIG. 14, the same elements as in the FIG. 11, FIG. 12, and FIG. 13 are denoted by the same reference symbols, and the reference symbol 24 denotes a light-shielding film, 25 denotes a polarizer, 26 denotes a backlight, 27 denotes an insulating layer, 28 denotes a first electrode layer, and 29 denotes a second electrode layer. As shown in FIG. 14, the light-shielding film 24 which is composed of a metal film is formed above the insulating substrate 1, and then the thin film transistor 22 is formed above the light-shielding film 24 in the related art. The light-shielding film 24 blocks lights from the backlight 26 to suppress the growth of leakage current. In the related art, however, while the leakage current from the semiconductor layer below the drain electrode can be suppressed, no measure was taken against electric charge flowing into the source line through a carrier developed in the semiconductor layer below the source line. Therefore, the electric charge coming into the source line causes the problem of decreasing picture quality. Also, since the light-shielding film 24 doubles as a gate electrode of the thin film transistor 22 in the related art, when the gate line (the light-shielding film 24) and another signal line are short-circuited due to contaminants produced during manufacturing processes and so on, picture problems such as line defects occur to lower manufacturing yield.
Further, when the semiconductor layer formed below the source line projects from the source line pattern due to the difference in etching quantity and so on, the part of the semiconductor layer which receives lights from the backlight becomes conductive. Therefore, the effective distance between the source line and the pixel electrode pattern becomes shorter, and a parasitic capacity between the lines increases. Further, the overlap width of the source line and an opposite electrode becomes effectively greater, and line loading capacity of the source line increases. Also, in a case where an extending pattern of the drain electrode is located near the source line or the gate line, when lights from the backlight come to the semiconductor layer lying below the pattern, the capacity between the drain electrode and the source electrode or between the drain electrode and the gate electrode increases.
In such a condition, when a so-called pulse lighting type that periodically repeats lights-up and lights-out is applied for the backlight, a leakage performance and/or a parasitic capacity vary between on-state and off-state of the backlight. Therefore, pixel potential and opposite electrode potential fluctuate with lighting condition of the backlight, and the fluctuation affects transmissivity of crystal liquid, causing to uneven picture or flicker.